Integrated circuits may include clock multiplier circuits. Generally, the clock multiplier circuit in an integrated circuit is used for multiplying the frequency of a clock input (or inputs) to the integrated circuit to generate one or more clocks for internal use within the integrated circuit. The clock multiplier may be used to allow lower frequency clocks to be supplied to the integrated circuit, while still allowing the higher frequency operation within the integrated circuit.
Clock multipliers are widely employed in modern semiconductor devices and are commonly implemented through the use of a phase lock loop (PLL) that includes analog circuits such as a phase/frequency detector and a charge pump to bias a voltage controlled oscillator (VCO) such that a divided version of the VCO matches a reference clock. Since PLLs require analog components, these multipliers cannot be built from a purely digital library that utilizes processing technology optimized for purely digital circuits. Furthermore, such multipliers have long acquisition times, usually on the order of hundreds to thousands of clock cycles. Moreover, PLLs use a large amount of area and power and require both design and verification resources.
A technique employed for digitally doubling a clock involves XORing a reference clock signal with the same signal delayed by 90 degrees (one quarter clock cycle) as is provided in “Fully Digital Clock Synthesizer”, Anderson et al. (U.S. Pat. No. 5,920,211), which is incorporated by reference herein. The XORed output will have a frequency which is twice the frequency of the reference clock signal. Ordinary circuit delay elements, however, vary widely with changing operating parameters such as voltage, temperature, and variances in integrated circuit processing. Thereby, the clock duty cycle will vary widely for the doubled clock.
Furthermore, the XOR method of clock doubling is also limited to obtaining a frequency which is twice the reference clock frequency. Thus, even if a method of adding a precise amount of delay (90 degrees) between the XOR inputs were devised, the frequency range achievable would be limited. At best, the frequencies which could be obtained from such a mechanism would be some power of two times the reference clock frequency.
The fully digital clock synthesizer of Anderson et al. provides a clock multiplier which may be implemented with only digital components and fabricated using only digital processes. The clock multiplier is capable of producing a frequency which is any whole number or fractional multiple of the input or reference clock frequency and it can obtain a precise duty cycle in the output clock signal. The fully digital clock synthesizer of Anderson et al., however, is limited in resolution by the minimum delay element in the delay cell string.
Thus, there is a need therefore for providing a fully digital clock synthesizer that provides highly accurate clocks without the need for any analog components, wherein the clock synthesizer is implemented with only digital components and fabricated using only digital processes. In addition, there is a need for a high resolution fully digital clock synthesizer that is not limited in resolution by the minimum delay element. Furthermore, there is a need to provide a clock multiplier capable of producing a frequency which is any whole number or fractional multiple of the input or reference clock frequency. Moreover, it would also be advantageous to obtain a precise duty cycle in the output clock signal.